BS (1996) from
Tuskegee University; MS (1999) in Electrical Engineering from
the University of Washington
Ph.D (2004) Electrical
and Computer Engineering (with a minor in applied physics) from
thesis: ; advisor
of Electrical and Computer Engineering at the University of Rochester
Selected Publications and Presentations:
- "An Efficient Hardware Interleaver for 3G Turbo Decod-
ing" (with K. Kornegay),
IEEE Radio and Wireless Commu- nications Conference (RAWCON)
Digest of Technical Papers, Boston MA, 2003.
- "A Compact Low-Energy Pass-Transistor Circuit Tech-nique
for Deep Submicron CMOS" (with K.
Kornegay), Proceedings of the 10th NASA Symposium on
VLSI Design, Albuquerque NM, 2002.
- · "A 1.3GSample/s 10-Tap Full-Rate Variable Latency
Self-Timed FIR Filter with Clocked Interfaces" (J. Tierno,
et.al), IEEE International Solid-State Circuits Conference (ISSCC)
Digest of Technical Papers, San Francisco CA, 2002.
- · "A 2.3GSample/s 10-Tap Digital FIR Filter for
Magnetic Recording Read Channels" (with S. Rylov, et.al),
IEEE International Solid-State Circuits Conference (ISSCC) Digest
of Technical Papers, San Francisco CA, 2001.
Recent Research Projects:
- Design of an 18-Bit Hybrid Binary Adder AchievingWorst-Case
Computation Times of .54 ns in a .25u process
- Development of a Gigahertz 9x9 Fast Booth Multiplier in a
references: Roger Guibinga; http://www.ece.rochester.edu/newsEvents/;